`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2020/11/11 11:55:35
// Design Name: 
// Module Name: display_driver
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

/*
 * input: clock@100MHz
 * output: selection signal
 * 		data_sel: which digit shall be on the data bus (2'b00 to 2'b11)
 *		digit_en[i]: enable signal of digit displays (corresponds with data_sel)
 */
module display_driver(
    input clk_i,  // 100MHz
    input [3:0] num3,
    input [3:0] num2,
    input [3:0] num1,
    input [3:0] num0,
	input [3:0] dots_ctrl,
	
	output [7:0] decoded_num,
    output reg [3:0] digit_en = 4'b0000
    );
    // 1kHz scanning speed
    wire clk_1khz;
    divider_1khz DIVIDER(clk_i, 1'b0, clk_1khz);
    
    // selects which digit is on the bus
    reg [1:0] data_sel = 2'b00;
    
    // the digit on the bus, not decoded
    reg [3:0] bus = 8'b0;
    
    // decoder: decodes the digit
    decoder_3_seg DECODER(bus, dots_ctrl[{data_sel[1], data_sel[0]}], decoded_num);

    always @(posedge clk_1khz) begin
       if (data_sel==2'b11) begin 
           data_sel <= 2'b00;
           digit_en <= 4'b0001;
           bus <= num0;
       end else if (data_sel==2'b10) begin
           data_sel <= 2'b11;
           digit_en <= 4'b1000;
           bus <= num3;
       end else if (data_sel==2'b01) begin
           data_sel <= 2'b10;
           digit_en <= 4'b0100;
           bus <= num2;
       end else if (data_sel==2'b00) begin
           data_sel <= 2'b01;
           digit_en <= 4'b0010;
           bus <= num1;
       end else begin
           data_sel <= 2'b00;
           digit_en <= 4'b0001;
           bus <= num0;
       end 
    end
endmodule
